(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the etching of contact openings in the manufacture of sub-micron MOSFETs.
(2) Background of the Invention and Description of Prior Art
The fabrication of integrated circuit chips comprises the formation of semiconductor devices within the surface of a single crystalline silicon wafer. The semiconductive elements of metal-oxide-silicon-field-effect-transistors (MOSFETs) are contained within the surface of the single crystalline substrate wafer and are formed by ion-implantation using the control electrode, a polysilicon gate formed over the substrate, as an implantation mask. The source and drain regions of the MOSFET are thereby self-aligned to the gate electrode.
Many variations of the principle of self alignment to the polysilicon gate have been developed to improve device performance and stability, in particular, the use of side walls along the edges of the polysilicon gate have permitted the tailoring of source and drain diffusions at the ends of the channel region to control short channel effects. These advances in MOSFET processing have resulted in high performance sub-micron sized devices of many types. The lightly-doped-drain (LDD) structure, used universally in sub-micron MOSFET technology, is a notable example of this side-wall tailoring.
The use of insulative sidewalls and caps over polysilicon conductors has also permitted the formation of self-aligned contacts (SAC) to MOSFET active elements. Self-alignment processing utilizes reactive-ion-etching (RIE) to anisotropically etch vertical walled openings, typically through insulative layers, such as silicon oxide and various silicate glasses.
Self-aligned-contacts can be made in various configurations. Typically an insulative sidewall is provided along the edge of the polysilicon gate electrode. The sidewall provides an insulative spacing between the contact and the polysilicon gate. Referring to FIG. 1 there is shown a cross section of a silicon wafer with two adjacent MOSFETs. The configuration shown here is typical of a well known design (DASH Cell) for a dynamic random access memory (DRAM) cell. The polysilicon gate electrodes 18 form the wordlines of the DRAM. The source/drain diffusions 12, 14 are formed by the widely used LDD process utilizing the sidewalls 27. In subsequent processing steps, storage capacitors are formed over the semiconductive elements 14 while a bitline contact is made to the semiconductive element 12.
The polysilicon word lines in this example have a tungsten silicide layer 20 and a thin silicon oxide layer 22 over them. The sidewalls 27 and a top protective layer 24 are formed of silicon nitride. These layers are formed and patterned by conventional modern processing techniques well known to those in the art. An insulative layer 28, for example silicon oxide is deposited over the wafer and planarized by any of several well known techniques, for example chemical mechanical polishing (CMP). An opening for the bitline contact is then defined using well known photolithographic processing, whereby a pattern is formed in a photoresist layer 30. The photomask opening can be made larger than the contact area at the silicon surface. The self-alignment feature permits a slight mis-alignment of the photomask because the contact at the silicon is determined by the nitride sidewall 27.
The wafer 10 is then subjected to an RIE processing step whereby the opening 32 for the bitline contact is etched in the insulative layer 28. The etchant gas and the RIE parameters are selected to provide vertical walls in the opening in the silicon oxide layer and a high silicon oxide etch rate selectivity, that is to say, a high silicon oxide to silicon nitride etch rate ratio. The opening illustrated in FIG. 1 was formed with an etch rate sensitivity so high that the nitride sidewalls 27 and the exposed upper portions of the nitride top cap 24 are imperceptibly etched.
Under conditions of inadequate etch rate selectivities the nitride sidewalls 27 and top nitride cap 24 etch at rates whereby the insulative spacing provided by these elements is reduced by erosion of the nitride, resulting in subsequent shorts between bitline and wordline. This is illustrate in FIG. 2 Where the upper corners 34 of the wordlines have been exposed.
Until recently, etch rate selectivities greater than about 8:1 were not attainable without sacrificing other important aspects such as etching anisotropy. In the current technology, where dimensional features are of the order of quarter micron, it becomes increasingly more difficult to achieve a sufficiently high etch rate selectivity for this contact opening etch without aggravating deleterious side effects, for example incomplete oxide removal at the base of the contact resulting in unacceptable contact resistance.
It is widely believed that polymer formation in an RIE plasma containing fluorocarbon etchants, is largely responsible not only for etching anisotropy but also for the etch rate selectivities. The polymer contains fluorine and carbon. In the case of silicon oxide etching, the polymer formed at the etching front is rapidly dissociated by the released oxygen. However, over regions of silicon nitride, the oxygen concentration is less and the polymer is not readily dissociated, thereby providing passivation of the silicon nitride.
In order to achieve the high etch rate sensitivity to achieve the profile shown in FIG. 1, it was necessary to utilize etchant gases and RIE parameters which provided a relatively high steady state polymer thickness. The residual polymer 36 is shown prior to its removal at the termination of the etching operation. Insufficient steady state polymer thickness leads to the profile shown in FIG. 2.
Bialock, et.al., U.S. Pat. No. 5,286,344 cites the use of high etch rate selectivities for silicon oxide over silicon nitride utilizing a continuous nitride layer beneath the oxide layer which acts as an etch stop. A single step etch process is used wherein the oxide/nitride etch rate selectivity of a conventional CF.sub.4, CHF.sub.3, Ar gas mixture is raised from 1.2:1 to 30:1 by the addition of CH.sub.2 F.sub.2. The increase in selectivity is attributed to polymer deposition over the nitride. The selection of the additive gas such as CH.sub.2 F.sub.2 is made according to a rule wherein the number of hydrogen atoms must be equal to or greater than the number of fluorine atoms.
Marks, et.al., U.S. Pat. No. 5,423,945 have found that reducing the fluorine content of the passivation polymer, and reducing the amount of free fluorine in the plasma, reduces the dissociation of the polymer. By adding a fluorine scavenger such as silicon or carbon ions to the plasma, the resultant polymer becomes carbon rich and is more resistant to dissociation. In an example, an etch rate selectivity of oxide to nitride of 15:1 was achieved by the use of a fluorine scavenger.
Dahm, et.al., U.S. Pat. No. 5,431,778 does not use halogenated hydrocarbon gases for etching silicon oxide. Instead gas mixtures containing combinations of F.sub.2, O.sub.2, CO.sub.2, HF, and CH.sub.4 are employed. CH.sub.4 or CO.sub.2 provides carbon for polymer formation over nitride regions increasing the selectivity. Although specific oxide/nitride selectivities are not cited, the extent of polymer formation is attributed to the amount of oxygen present in the chamber.
One of the problems incurred during etching of very small (&lt;0.35 .mu.m) contact openings at high selectivities is that the heavy polymer formation interferes with the proper clearing of oxide at the base of the contact opening to expose the silicon surface. The residual oxide in the opening results in inconsistent and unacceptably high contact resistance. This problem is not addressed by any of the references cited.
FIG. 3 shows an profile of a contact opening which has been etched using high etch rate selectivitities comparable to those used to attain the profile shown in FIG. 1. However, the width of the contact opening 40 is less than or equal to 0.15 .mu.m. The steady state polymer thickness pinches off access of the reactant gases to the underlying oxide layer 38, resulting in incomplete clearance of oxide. In an intermediate case, the etchant may penetrate the oxide layer in the center but be pinched off before sufficient area of the silicon surface was cleared leaving pockets of residual oxide around the periphery of the contact opening. The residual oxide in the opening will cause an open or unacceptable and erratic high resistance contacts.
The need to consider reduction of the rate of polymer formation as the etch front enters the narrow region of the contact opening between the nitride sidewalls arises when the steady state polymer thickness comes within range of the width of the contact opening. Steady state polymer thicknesses required to achieve etch rate selectivities of oxide to nitride of the order of 15:1, become intrusive when contact openings are less than 0.15 .mu.m in their smallest dimension.